As various electronic devices including a personal computer, a digital camera, and a mobile phone progress toward downsizing and higher performance, requirements are rapidly increasing for further downsizing, thinning, and higher density in a semiconductor device. Accordingly, it is desired to develop a photosensitive insulating material, a stacked semiconductor apparatus, and a method for manufacturing the same that can cope with an increase in surface area of a substrate for the sake of higher productivity, and can be used in high density mounting technologies including a chip size package or a chip scale package (CSP) and a three-dimensional lamination.
Conventionally, examples of a method for manufacturing a semiconductor apparatus by connecting an electrode formed on a semiconductor device to an interconnect pattern formed on a substrate includes connection between the semiconductor device and the substrate by wire bonding. However, the connection between the semiconductor device and the substrate by wire bonding requires a space for drawing metal wire on the semiconductor device. This makes the apparatus large, resulting in difficulty downsizing.
On the other hand, Patent Documents 1 and 2 disclose examples of placing a semiconductor device on a circuit board and methods for placing three-dimensionally stacked semiconductor devices on a circuit board without wire bonding.
Patent Document 1 discloses an example of the method for manufacturing a semiconductor apparatus having a semiconductor device, such as light-emitting device and light-receiving device. In this example, as shown in FIG. 25, a semiconductor apparatus 50 is manufactured by connecting an aluminum (Al) electrode pad 55 to a redistribution pattern 52 via a through electrode 56 and connecting the redistribution pattern 52 to a redistribution pattern 57 on a circuit board 53 via a solder bump 58. A device-forming layer 59 and multiple Al electrode pads 55 are formed on the upper surface of the semiconductor apparatus. A through hole 54 penetrating the semiconductor apparatus is provided between the Al electrode pad 55 and the redistribution pattern 52 by dry etching. The through electrode 56 is formed within the through hole 54 by plating with copper. The device-forming layer 59 is placed on the upper surface of the semiconductor apparatus to emit or receive light.
This method does not require the connection between the semiconductor device 51 and the circuit board 53 by wire bonding, but requires rewiring on the semiconductor apparatus and placing the solder bump. Thus, fine rewiring and highly dense solder bump are required with downsizing of the semiconductor apparatus, resulting in difficulty in practice.
Patent Document 2 discloses a method for manufacturing a semiconductor apparatus useful for three-dimensional stacking of multiple semiconductor devices and also discloses an exemplary structure in which a semiconductor device 180 and a semiconductor device 280 are stacked, as shown in FIG. 26.
Each semiconductor device (180, 280) to be stacked is connected to a substrate (110, 210) including a core material (150, 250), a through electrode (140, 240), and an interconnect layer (157, 257) via a solder bump (170, 270) and a pad (182, 282) of the semiconductor device. The interconnect layer (157, 257) includes a mounting pad (165, 265), a connecting pad (164, 264), and an interconnect (266). A space between the outermost surface of the substrate (110, 210) and the semiconductor device (180, 280) is filled with an under fill (184, 284). Patent Document 2 discloses a method for connecting and stacking, via solder bumps (174, 176), such substrates each connected to the semiconductor device.
However, Patent Document 2, in which the semiconductor device is connected to the circuit board via a solder bump, also considerably requires highly dense solder bumps with downsizing of the semiconductor device as in Patent Document 1, resulting in difficulty in practice. In addition, the through electrode provided in the second substrate 210 is difficult to be formed because this formation requires complicated steps.
Patent Document 3 discloses examples of a semiconductor apparatus placed on a circuit board, a method for manufacturing the same, a semiconductor apparatus including stacked semiconductor devices, and a method for manufacturing the same. Patent Document 3 discloses a semiconductor apparatus, as shown in FIG. 27, including an organic substrate 301, through vias 304 which penetrate the organic substrate 301 in its thickness direction, external electrodes 305b and internal electrodes 305a provided on both faces of the organic substrate 301 and electrically connected to the through vias 304, a semiconductor device 302 mounted on one main surface of the organic substrate 301 via a bonding layer 303, with a device circuit surface thereof facing upward, an insulating material layer 306 for encapsulating the semiconductor device 302 and a periphery thereof, a metal thin film wiring layer 307 provided in the insulating material layer 306, with a part of this metal thin film wiring layer being exposed on an external surface, metal vies 310 electrically connected to the metal thin film wiring layer 307, a wiring protective film 311, and external electrodes 309 formed on the metal thin film wiring layer 307, in which the metal thin film wiring layer 307 is structured such that the electrodes disposed on the device circuit surface of the semiconductor device 302, the internal electrodes 305a, the metal vies 310, and the external electrodes 309 formed on the metal thin film wiring layer 307 are electrically connected. Patent Document 3 also discloses methods for manufacturing this semiconductor apparatus placed on a circuit board and a semiconductor apparatus including multiple semiconductor devices that are stacked. The method of Patent Document 3 does not require to form many solder bumps on the semiconductor device, and thus can form many electrodes on the semiconductor device with high density, thereby achieving downsizing of the semiconductor apparatus.
However, a structure of the semiconductor apparatus disclosed in Patent Document 3 still has difficulty in processing to form the through vias 304 toward the circuit board. Although processing with a micro-hole drill and processing with laser are disclosed therein, these processing techniques are still unsatisfactory for miniaturization of the semiconductor apparatus to be expected.
In addition, Patent Document 3 discloses, as shown in FIG. 28, patterning a photosensitive resin layer 316 applied on the surface of the semiconductor device to form openings 317 for vias 308 to be formed on the semiconductor device 302. The insulating material layer 306 on the periphery of the semiconductor device is formed by, for example, spin coating. In practice, however, this method requires complicated steps of providing the resin twice for coating the semiconductor device 302 with the photosensitive resin layer 316 and for forming the insulating material layer 306 on the periphery of the semiconductor device 302. Moreover, when spin coating is carried out to provide the insulating material layer 306, a height of a semiconductor device 302 is important. In case that the height exceeds several tens of μm, it is practically difficult to get over the semiconductor device and then provide the insulating material layer 306 by spin coating without voids. This publication also discloses an example in which the vias 308 of the photosensitive resin layer 316 and the metal vias 310 of the insulating material layer 306 are separately formed by different steps, and an example in which the metal vias 310 are processed with laser, but these steps are complicated and not rational. The publication also discloses that the photosensitive resin layer 316 and the insulating material layer 306 can be simultaneously provided on the periphery of the semiconductor device 302 and on the circuit surface, but fails to disclose illustrative examples of this method. It is difficult to provide these resin layers without generating voids on the periphery of the semiconductor device. Furthermore, the publication also discloses that the vias 308 of the photosensitive resin layer 316 and the metal vias 310 of the insulating material layer 306 can be simultaneously formed, but fails to disclose illustrative examples of this method.